As is well known, sophisticated techniques are currently employed in the formation of bipolar transistors, especially of those intended for applications which involve high switching frequencies. These techniques provide, for instance, for the isolation of adjacent components, using either a dielectric material or so-called trenches; the use of multiple polysilicon layers; self-alignment using dielectric material spacers which consist of a single layer of SiO.sub.2 or of composite materials; and high-speed thermal treatments called RTPs (Rapid Thermal Processes), to be applied at various stages of the fabrication process.
Reference will be made herein, by way of example, to the forming process for a transistor formed with DPSSAT (Double Polysilicon Spacer Self-Aligned Transistor) technology, wherein a double layer of polysilicon is used, with self-alignment being ensured by spacers.
The structure and performance of a bipolar transistor for high frequencies, of this kind, are described, for example, in an article "Bipolar Device Design for High-density High-performance Applications" by P. C. Hunt, Proceedings of IEDM, 1989, pages 791-794.
An example of a conventional structure of a high-frequency bipolar transistor, such as that described in the above article, is illustrated by FIG. 1. A single component has been shown therein, which by way of example only is a transistor of NPN type, i.e. of the type more frequently used in integrated circuits.
FIG. 1 shows a cross-section drawn, not to scale, through a chip of a semiconductor material which includes a substrate, denoted by 1, of the P-type, a buried layer 2 of the N+ type, and an epitaxial layer 3 of the N-type. The transistor is isolated laterally from adjacent components or structures, not shown in the Figure, by so-called isolation trenches, denoted by 4, which define peripherally the region wherein the transistor is formed. The trenches 4 consist of a dielectric multilayer. In particular, they include a central region 5 of polysilicon which extends vertically down to the substrate 1 from the surface 6 of the chip, a layer 7 of silicon nitride which surrounds the region 5 completely but for its portion facing the surface 6, and an outermost layer of thermal silicon oxide 8 to complete the construction of the trenches 4.
Field oxide regions 9 and 10, define the active area zones--i.e. zones where the epitaxial layer 3 is not covered by the field oxide--and extend through the surface 6. In particular a first of these regions 9 is formed over the trenches 4, the second region 10 is located in an intermediate zone and defines two separate active area zones 11 and 12 wherein the contacts are formed, respectively on the left and right sides, as viewed in FIG. 1, of the field oxide 10. Included in the epitaxial layer 3 beneath zone 12 is a so-called sinker region 13 of the N+ type which is extended to the buried layer 2.
A first polysilicon layer 14, doped N+ in zone 12, contacts the monocrystalline silicon, specifically in the sinker region 13. A metal layer 15, forming the collector contact, is in electric contact with the first polysilicon layer 14 through an opening in an overlying oxide layer 16.
Formed in the active area zone 11 is a first shallow base region 17 doped P. A second base region 18, called an extrinsic base region, is shown by the two P+ regions 18 in cross-sectional view of FIG. 1. The second base region 18 surrounds the first base region 17. The first polysilicon layer 14, doped P+, is also formed over the base regions 18, in contact therewith, and one end of the layer is extended partly over the field oxide region 10 to contact a base metallization 20.
An emitter opening or window is defined through the layers 16 and 14, above the first base region 17. The lateral corner edges of this opening are covered with two symmetrical L-shaped portions of an insulating material, called the side spacers. Both spacers comprise, of preference, a layer 21 of silicon oxide and a layer 22 of silicon nitride. A second polysilicon layer 23, doped for conductivity of the N+ type, contacts the surface 6 of the chip at the exposed portions of the emitter window.
As shown in FIG. 1, a surface region 24 formed by diffusion from the polysilicon layer 23, represents the emitter active region. The region 24 is fully included within the first base region 17. Thus, a base region in the proper sense of the word, or so-called intrinsic base region 19, can be defined inside the first base region 17, underneath the emitter region 24.
The second polysilicon layer 23, being U-shaped, covers the spacers 21 and 22, and extends partly over the silicon oxide layer 16. Next, the second polysilicon layer 23 is overlaid by an emitter metallic contact 25.
The above technology yields transistors which have excellent dynamic performance, with cutoff frequencies in excess of 20 GHz, propagation times on the order of 40 ps, and power-by-speed products of about 40 fJ.
But applications of more recent acquisition demand still better performance, especially higher cutoff frequencies, and need shorter propagation times. To this aim, it is necessary that the distributed base resistance r.sub.bb, which accounts for several resistive contributions between the intrinsic base active region 19 and the base contact 23, be first reduced. In this way, the charging and discharging times of the capacitances of the base-emitter junction can be shortened.
To further improve dynamic performance, the thickness of the intrinsic base must be reduced; propagation time, which is tied to this quantity by quadratic law, can thus be reduced considerably.
To reduce the intrinsic base thickness 19, and hence the junction depth, the dopant depth of penetration must be reduced. Specifically in a standard process, the depth of the intrinsic base region 19 at the end of the process is attained in consecutive steps. The process provides for the implanting of dopant ions, such as boron B+ in the instance of an NPN transistor, followed by thermal treatments in the oven and/or RTP processing.
A first attempt at reducing the dopant penetration included suppressing, or at least reducing the temperatures and durations of the after-implantation thermal treatments. In this way, a dopant concentration profile is obtained which differs only slightly from the earlier mentioned implanted profile of FIG. 1.
In order to reduce the dopant penetration during the implanting step, the most up-to-date processes adopt low-energy implantation methods. However, account must be taken of the channeling phenomenon, which restricts the applicability of this approach.
To compensate or attenuate this phenomenon, several solutions have been adopted such as the introduction of pre-amorphizing techniques and/or the use of heavier, less-penetrating molecules; e.g., molecules of BF.sub.2 have been used for NPN transistors. Nevertheless, serious limitations still militate against attaining shallower intrinsic base regions.